In the step of forming contact plugs of DRAMs or in the step of forming floating gates in flash memories, the CMP of a silicon film is used, examples of the film including a polysilicon film, and an amorphous silicon film. About such semiconductor elements, requirements for the planarity thereof after CMP have been becoming severer because of promoting miniaturization. Thus, it has been becoming difficult that conventional slurries for silicon film polishing give a sufficient planarity.
As illustrated in FIG. 5, in the step of forming contact plugs in DRAMs, an inter-gate insulating film 7 buried between gate structures 3 is etched to make openings, thereby making contact holes. Thereafter, an electroconductive material 8, for contact plug, is deposited thereon. As the contact plug electroconductive material 8, polysilicon, amorphous silicon or the like is used. Next, unnecessary portions of the contact plug electroconductive material 8 are removed by CMP to form the contact plugs, as illustrated in FIG. 6. In this CMP step, in order for the unnecessary portions of the contact plug electroconductive material 8 not to remain on the gate structures 3 or on the inter-gate insulating film 7, it is necessary to perform over-polishing. At this time, in the contact hole regions, which are opening regions in the inter-gate insulating film 7, the contact plug electroconductive material 8 is excessively polished so that the tops of the contact plugs turn into a concave form. Thus, dishing or erosion is generated to damage the planarity. A deterioration in the planarity by the dishing results in a scattering in the height of the contact plugs, so as to cause a fall in the margin of lithography, polish residues in the CMP, and others. Thus, a fall in the yield is caused.
The following will describe a method for forming floating gates in flash memories by use of CMP. Any figure group out of FIG. 7 to FIG. 9 illustrates a plan view and sectional views in each of steps of the formation of the floating gates by use of CMP. In the sectional views, cross sections of a cross section 1 and a cross section 2 shown in the plan view, which are taken along two directions, are illustrated.
A diffusion layer (not illustrated) is formed on a surface of a silicon substrate 1, and subsequently an element isolation insulating film 20 that is formed on the whole of the substrate surface is worked by dry etching, using a photoresist pattern as a mask, to remove unnecessary portions of the resist. The thickness of the element isolation insulating film 20 is from about 50 to 200 nm. In FIG. 7 is illustrated a state that a gate insulating film 2 is afterwards formed on the uncovered surface of the silicon substrate 1.
FIG. 8 illustrate cross sections after a silicon film 30 for floating gates is formed by CVD (chemical vapor deposition). For the silicon film 30, polysilicon or amorphous silicon is used. The film thickness of the silicon film 30 is set to about two times that of the element isolation insulating film 20. Also after the silicon film 30 is formed, steps of the pattern of the element isolation insulating film 20 are kept as they are. When a photoresist pattern for working the silicon film 30 is formed in the state that the film 20 has these steps, a poorness in the resolution of the pattern, or the like is easily caused. In the case of semiconductor devices made minute, the poorness or the like causes a fall in the yield thereof. As illustrated in the cross section 1 in FIG. 8(b), the silicon film 30 is made into a conformal form; therefore, the film thickness of side wall portions of the pattern of the element isolation film 20 becomes large in the vertical direction. For this reason, when the silicon film is worked by anisotropic dry etching, an etch residue is easily generated in the side wall portions of the pattern of the element isolation insulating film 20 to cause a short circuit easily between gates. In order to remove this etch residue, over-etching is performed; however, when the period therefor is made long, the gate insulating film 2, which is thin, is damaged so that the reliability of the device is declined. In the case of semiconductor devices made minute, such a problem is serious.
In order to avoid such a problem, suggested is a method of removing convexes of the silicon film 30 by CMP. FIG. 9 illustrate a state of the silicon film 30 after the CMP. At this time, the convexes of the silicon film 30 regions on the element isolation insulating film 20 are removed. It is however necessary to make the element isolation insulating film 20 into a covered state. The remaining film thickness of the silicon film 30 regions on the element isolation insulating film 20 is about ¼ to ½ of the film thickness of the element isolation insulating film 20.
In the state that the silicon film 30 is planarized in this manner, a pattern of a photoresist 40 is formed (FIG. 10) and the workpiece is worked by anisotropic dry etching (FIG. 11), thereby making it possible to avoid a poorness in the resolution of the photoresist pattern, a short circuit between the gates on the basis of the etch residue, a decline in the reliability of the gate insulating film by over-etching, and other problems.
In a CMP step of a silicon film in a semiconductor element, the following two cases are adopted: a case where the CMP is performed until an underlay (for example, a gate structure and an inter-gate insulating film) is made uncovered in the step of forming contact plugs, as descried above; and a case where the polishing is stopped after irregularities in the substrate surface are cancelled in the step of forming floating gates and before an underlay (for example, an element isolation insulating film) thereof is made uncovered. About any use application, requests for the planarity of a polished surface have been increasingly becoming severer in order to make its elements minuter. Therefore, it has been intensely desired to develop a slurry having a better step-canceling performance, over-etching resistance and performance of controlling the remaining film thickness than conventional slurries.
Japanese Patent No. 3457144 discloses, as a silicon-film-polishing slurry, a composition for polysilicon polishing which contains a basic organic compound. This polishing composition has a large polishing rate for a polysilicon film. Thus, the polishing rate thereof is larger in the polishing of a polysilicon film than in the polishing of a silicon dioxide film. However, the planarity of the surface polished therewith is insufficient. Thus, it is difficult that the slurry copes with LSIs made minuter. Japanese Patent Application Laid-Open (JP-A-) No. 2005-175498 discloses, a different silicon-film-polishing slurry, a polishing slurry composition containing a nonionic surfactant to improve the planarity of a polished surface. However, this polishing slurry composition is expected not to give a sufficient planarity, either, since the capability of the nonionic surfactant to protect the surface of a silicon film is insufficient.
About the silicon-film-polishing slurries described in the documents, it is presupposed that CMP is performed until an oxide film or nitride film as an underlay is made uncovered. Thus, it is difficult to control the remaining film thickness when CMP is stopped without making the underlay uncovered.